1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more specifically to efficient read methods in such devices with reduced power consumption.
2. Description of Related Art
Power consumption in integrated circuit memory devices is a design concern in many applications, including memory for small portable devices that rely on battery power or other sources of limited power, and memory for systems that otherwise require power efficient operation.
One source of power consumption in memory devices during a read operation arises from bit line pre-charge operations, used to set up a bit line for a read. Typical structures used for these purposes are illustrated in U.S. Pat. No. 6,219,290, entitled MEMORY CELL SENSE AMPLIFIER, invented by Chang et al.; U.S. Pat. No. 6,498,751, entitled FAST SENSE AMPLIFIER FOR NONVOLATILE MEMORIES, invented by Ordonez, et al.; U.S. Pat. No. 6,392,447, entitled SENSE AMPLIFIER WITH IMPROVED SENSITIVITY, invented by Rai et al.; and U.S. Pat. No. 7,082,061, entitled MEMORY ARRAY WITH LOW POWER BIT LINE PRE-CHARGE, invented by Chou et al.
Basically the set up procedures in the prior art seek to first discharge the bit lines in an array to a common voltage such as ground, and then pre-charge selected bit lines for a read operation. Since the bit lines have relatively large capacitance, the pre-charging and discharging operations can require significant current, and substantial power to produce the current. When a large number of bit lines are being operated in parallel, such as in modern devices that include 64 or more parallel sense amplifiers, the power needed to generate this current can be even more significant.
It is desirable therefore to provide read methods and systems that conserve power during read operations.